Cosiatec Solutions exudes dynamism in providing softwarevconsultanc y, human capital solutions, executive search services and professional recruitment solutions serving the fast growing specialized segments of information technology, semiconductor, microelectronics, biomedical, banking & financial institutions in Asia Pacific.
Our Client is a leading provider of Process-Design Integration technologies for integrated circuit is looking for Semiconductor IC Layout engineer.
Developing and supporting in-house layout generation tools for Characterization Vehicle test chips within the Cadence Design Framework (C++, Qt, Cadence ).
Developing and supporting in-house layout verification tools (LVS, DRC) based on Cadence/Assura, Mentor/Calibre, and Magma/Quartz.
Developing and maintaining test-suites for quality assurance of in-house layout generation and verfication tools.
Writing and maintaining internal documentation and giving training classes to transfer knowledge effectively to internal customers.
Required skills and experience:
C++ programming language.
Excellent computer skills (UNIX/Linux) .
Experience with at least one scripting language, e.g. Perl.
Excellent written and oral communication skills.
Highly professional, self-motivated and self-managed.
Job desirables:
Semiconductor/ CMOS fundamentals are present.
Experience with CAD systems.
Experience with Qt/C++ Development Framework.
Please email your detailed resume in word format and indicate last drawn salary & expected salary to: resumes@cosiatec. com
Only shortlisted candidates will be notified.
All information will be treated with strictest confidence.
CosiaTec maintains a strict confidentiality policy on all personal data submitted by all candidates and is committed to the protection of their personal information. CosiaTec will not release such information to anyone without the prior consent of the candidates.
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